View MAX106CHC_1990009.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max106 pecl-compatible, 600msps, 8-bit analog-to- digital converter (adc) allows accurate digitizing of ana- log signals with bandwidths to 2.2ghz. fabricated on maxim? proprietary advanced gst-2 bipolar process, the max106 integrates a high-performance track/hold (t/h) amplifier and a quantizer on a single monolithic die. the innovative design of the internal t/h, which has an exceptionally wide 2.2ghz full-power input bandwidth, results in high, 7.6 effective bits performance at the nyquist frequency. a fully differential comparator design and decoding circuitry combine to reduce out-of- sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance of one error per 10 27 clock cycles. unlike other adcs, which can have errors that result in false full- or zero-scale out- puts, the max106 limits the error magnitude to 1lsb. the analog input is designed for either differential or sin- gle-ended use with a ?50mv input voltage range. dual, differential, pecl-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. the pecl outputs can be operated from any supply between +3v to +5v for compatibility with +3.3v or +5v referenced systems. control inputs are provided for interleaving additional max106 devices to increase the effective system sampling rate. the max106 is packaged in a 25mm x 25mm, 192-con- tact enhanced super-ball-grid array (esbga), and is specified over the commercial (0? to +70?) temperature range. for a pin-compatible higher speed upgrade, refer to the max104 (1gsps) and max108 (1.5gsps) data sheets. applications digital rf/if signal processing direct rf downconversion high-speed data acquisition digital oscilloscopes high-energy physics radar/ecm systems ate systems features ? 600msps conversion rate ? 2.2ghz full-power analog input bandwidth ? 7.6 effective bits at f in = 300mhz (nyquist frequency) ? ?.25lsb inl and dnl ? 50 differential analog inputs ? ?50mv input signal range ? on-chip, +2.5v precision bandgap voltage reference ? latched, differential pecl digital outputs ? low error rate: 10 -27 metastable states ? selectable 8:16 demultiplexer ? internal demux reset input with reset output ? 192-contact esbga ? pin compatible with faster max104/max108 max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ________________________________________________________________ maxim integrated products 1 19-1486; rev 0; 7/99 part MAX106CHC 0? to +70? temp. range pin-package 192 esbga typical operating circuit appears at end of data sheet. ordering information esbga top view max106 192-contact esbga ball assignment matrix esbga is a trademark of amkor/anam.
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc a = v cc i = v cc d = +5.0v ?%, v ee = -5.0v ?%, v cc o = +3.0v to v cc d, refin connected to refout, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc a to gnda .........................................................-0.3v to +6v v cc d to gndd.........................................................-0.3v to +6v v cc i to gndi ............................................................-0.3v to +6v v cc o to gndd ........................................-0.3v to (v cc d + 0.3v) auxen1, auxen2 to gnd .....................-0.3v to (v cc d + 0.3v) v ee to gndi..............................................................-6v to +0.3v between gnds......................................................-0.3v to +0.3v v cc a to v cc d .......................................................-0.3v to +0.3v v cc a to v cc i.........................................................-0.3v to +0.3v pecl digital output current ...............................................50ma refin to gndr ........................................-0.3v to (v cc i + 0.3v) refout current ................................................+100? to -5ma iconst, iptat to gndi .......................................-0.3v to +1.0v ttl/cmos control inputs (demuxen, divselect) ....................-0.3v to (v cc d + 0.3v) rstin+, rstin- ......................................-0.3v to (v cc o + 0.3v) vosadj adjust input ................................-0.3v to (v cc i + 0.3v) clk+ to clk- voltage difference..........................................?v clk+, clk-.....................................(v ee - 0.3v) to (gndd + 1v) clkcom.........................................(v ee - 0.3v) to (gndd + 1v) vin+ to vin- voltage difference ............................................?v vin+, vin- to gndi................................................................?v continuous power dissipation (t a = +70?) 192-contact esbga (derate 61mw/? above +70?) ...4.88w (with heatsink and 200lfm airflow, derate 106mw/? above +70?) ....................................8.48w operating temperature range MAX106CHC........................................................0? to +70? operating junction temperature.....................................+150? storage temperature range .............................-65? to +150? t a = +25 c referenced to gndr 0 < i source < 2.5ma driving refin input only vin+ and vin- to gndi, t a = +25? vosadj = 0 to 2.5v signal + offset w.r.t. gndi t a = +25 c no missing codes guaranteed conditions k 45 r ref reference input resistance mv 5 ? refout reference output load regulation v 2.475 2.50 2.525 refout reference output voltage lsb ? ?.5 input v os adjust range k 14 25 r vos input resistance (note 2) ppm/? 150 tc r input resistance temperature coefficient lsb -0.5 ?.25 0.5 inl integral nonlinearity (note 1) bits 8 res resolution 49 50 51 r in input resistance v ?.8 v cm common-mode input range mvp-p 475 500 525 v fsr full-scale input range (note 1) lsb -0.5 ?.25 0.5 dnl differential nonlinearity (note 1) codes none missing codes units min typ max symbol parameter accuracy analog inputs v os adjust control input reference input and output
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc a = v cc i = v cc d = +5.0v ?%, v ee = -5.0v ?%, v cc o = +3.0v to v cc d, refin connected to refout, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) clk+ and clk- to clkcom, t a = +25? conditions ppm/? 150 tc r input resistance temperature coefficient 48 50 52 r clk clock input resistance units min typ max symbol parameter (note 10) (note 9) vin+ = vin- = ?.1v v ih = 2.4v v il = 0 db 40 68 psrr- negative power-supply rejection ratio (note 8) db 40 73 psrr+ positive power-supply rejection ratio (note 8) db 40 68 cmrr common-mode rejection ratio (note 7) w 5.25 p diss power dissipation (note 6) output supply current (note 6) ma 75 115 i cc o ma 205 340 i cc d digital supply current ma -290 -210 i ee negative input supply current ma 108 150 i cci positive input supply current ma 480 780 i cca positive analog supply current v 0.8 v il low-level input voltage v 2.0 v ih high-level input voltage v -1.810 -1.620 v ol digital output low voltage v -1.025 -0.880 v oh digital output high voltage v -1.475 v il digital input low voltage ? 50 i ih high-level input current ? -1 1 i il low-level input current v -1.165 v ih digital input high voltage clock inputs (note 3) ttl/cmos control inputs (demuxen, divselect) demux reset input (note 4) pecl digital outputs (note 5) power requirements
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 4 _______________________________________________________________________________________ f in = 600mhz f in = 500mhz f in = 125mhz f in = 300mhz f in = 600mhz f in = 600mhz f in = 125mhz f in = 300mhz f in = 125mhz f in = 300mhz conditions 56.7 db 57.4 sfdr 600 spurious-free dynamic range -67.5 -63.0 -67.5 thd 125 -56.5 -52.0 -56.5 thd 300 -56.1 db -57.0 thd 600 total harmonic distortion (note 12) 47.4 44.2 47.4 snr 125 47.1 43.8 47.1 snr 300 46.8 v/v 1.1:1 vswr analog input vswr ghz 2.2 bw -3db analog input full-power bandwidth db 46.8 snr 600 signal-to-noise ratio (no harmonics) 7.74 7.4 7.74 enob 125 7.65 bits 7.63 enob 600 7.62 7.3 7.65 enob 300 effective number of bits (note 11) units min typ max symbol parameter f in = 125mhz f in = 300mhz f in 1 = 124mhz, f in2 = 126mhz, at -7db below full scale f in = 125mhz f in = 300mhz 63.0 69.9 sfdr 125 57.4 52.0 57.5 sfdr 300 db -61.8 imd two-tone intermodulation 48.4 46.3 48.4 sinad 125 47.8 69.9 db 47.7 sinad 600 signal-to-noise ratio and distortion (note 11) 47.6 45.7 47.8 sinad 300 f in = 600mhz differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended differential single-ended f in = 600hz differential single-ended differential single-ended differential single-ended ac electrical characteristics (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 600msps, f in at -1dbfs, t a = +25?, unless otherwise noted.) vosadj control input open lsb -1.5 0 1.5 v os transfer curve offset analog input dynamic specifications
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier _______________________________________________________________________________________ 5 conditions units min typ max symbol parameter 20% to 80%, c l = 3pf 20% to 80%, c l = 3pf 20% to 80%, c l = 3pf figure 17 figure 17 figure 15 figure 15 figure 4 figure 17 ps 220 t rdready dready rise time ps 360 t fdata data fall time ps 420 t rdata data rise time ps -50 150 350 t pd2 dready to data propagation delay (note 14) ns 2.2 t pd1 clk to dready propagation delay ps 0 t hd reset input data hold time (note 13) ps 0 t su reset input data setup time (note 13) ps < 0.5 t aj aperture jitter ps 100 t ad aperture delay div1, div2 modes div1, div2 modes 20% to 80%, c l = 3pf 9.5 clock cycles 8.5 t pda auxiliary port pipeline delay clock cycles 7.5 t pdp primary port pipeline delay ps 180 t fdready dready fall time ac electrical characteristics (continued) (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 600msps, f in at -1dbfs, t a = +25?, unless otherwise noted.) note 1: static linearity parameters are computed from a ?est-fit?straight line through the code transition points. the full-scale range (fsr) is defined as 256 slope of the line. note 2: the offset control input is a self-biased voltage divider from the internal +2.5v reference voltage. the nominal open-circuit voltage is +1.25v. it may be driven from an external potentiometer connected between refout and gndi. note 3: the clock input? termination voltage can be operated between -2.0v and gndi. observe the absolute maximum ratings on the clk+ and clk- inputs. note 4: input logic levels are measured with respect to the v cc o power-supply voltage. note 5: all pecl digital outputs are loaded with 50 to v cc o - 2.0v. measurements are made with respect to the v cc o power- supply voltage. note 6: the current in the v cc o power supply does not include the current in the digital output? emitter followers, which is a func- tion of the load resistance and the v tt termination voltage. note 7: common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the common-mode voltage, expressed in db. note 8: measured with the positive supplies tied to the same potential, v cc a = v cc d = v cc i. v cc varies from +4.75v to +5.25v. note 9: v ee varies from -5.25v to -4.75v. note 10: power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power supply voltage, expressed in db. note 11: effective number of bits (enob) and signal-to-noise plus distortion (sinad) are computed from a curve fit referenced to the theoretical full-scale range. 7.5 msps 600 f max maximum sample rate figure 17 ns 0.75 t plw clock pulse width low figure 17 ns 0.75 5 t pwh clock pulse width high timing characteristics figures 6, 7, 8 figures 6, 7, 8 div4 mode div4 mode
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 6 _______________________________________________________________________________________ typical operating characteristics (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 600msps, t a = +25?, unless other- wise noted.) 8.00 10 100 1000 effective number of bits vs. analog input frequency (single-ended analog input drive) max106 toc01 analog input frequency (mhz) enob (bits) 6.75 6.50 7.25 7.50 7.00 7.75 -6dbfs -1dbfs -12dbfs 8.00 10 100 1000 effective number of bits vs. analog input frequency (differential analog input drive) max106 toc02 analog input frequency (mhz) enob (bits) 6.75 6.50 7.25 7.50 7.00 7.75 -6dbfs -1dbfs -12dbfs 50 10 100 1000 signal-to-noise plus distortion vs. analog input frequency (single-ended analog input drive) max106 toc03 analog input frequency (mhz) sinad (db) 47 48 46 49 -1dbfs -12dbfs -6dbfs 50 10 100 1000 signal-to-noise plus distortion vs. analog input frequency (differential analog input drive) max106 toc04 analog input frequency (mhz) sinad (db) 47 48 46 49 -1dbfs -12dbfs -6dbfs 50 10 100 1000 signal-to-noise ratio vs. analog input frequency (single-ended analog input drive) max106 toc05 analog input frequency (mhz) snr (db) 30 38 42 34 46 -1dbfs -12dbfs -6dbfs 50 10 100 1000 signal-to-noise ratio vs. analog input frequency (differential analog input drive) max106 toc06 analog input frequency (mhz) snr (db) 30 38 42 34 46 -6dbfs -1dbfs -12dbfs note 12: total harmonic distortion (thd) is computed from the first five harmonics. note 13: guaranteed by design with a reset pulse width of one clock period or longer. note 14: the dready to data propagation delay is measured from the 50% point on the rising edge of the dready signal (when the output data changes) to the 50% point on a data output bit. this places the falling edge of the dready signal in the middle of the data output valid window, within the differences between the dready and data rise and fall times, which gives maximum setup and hold time for latching external data latches.
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier _______________________________________________________________________________________ 7 75 10 100 1000 spurious-free dynamic range vs. analog input frequency (differential analog input drive) max106 toc10 analog input frequency (mhz) sfdr (db) 50 60 65 55 70 -12dbfs -6dbfs -1dbfs 8.00 100 600 effective number of bits vs. clock frequency max106 toc11 clock frequency (mhz) enob (bits) 6.75 6.50 7.25 7.50 7.00 7.75 f in = 125mhz, -1dbfs 6.50 7.00 6.75 7.50 7.25 7.75 8.00 -12 -8 -6 -4 -10 -20246810 effective number of bits vs. clock power max106toc12 clock power per side (dbm) enob (bits) single-ended clock drive differential clock drive f in = 125mhz, -1dbfs 6.50 7.00 6.75 7.50 7.25 7.75 8.00 4.50 5.30 4.70 5.50 4.90 5.10 effective number of bits vs. v cc i = v cc a = v cc d max106toc13 v cc (v) enob (bits) f in = 125mhz, -1dbfs 65 67 66 70 69 68 71 72 74 73 75 spurious-free dynamic range vs. v cc i = v cc a = v cc d max106 toc16 v cc (v) sfdr (db) 4.50 5.30 4.70 5.50 4.90 5.10 f in = 125mhz, -1dbfs 6.50 7.00 6.75 7.50 7.25 7.75 8.00 -4.50 -5.30 -4.70 -5.50 -4.90 -5.10 effective number of bits vs. v ee max106toc14 v ee (v) enob (bits) 55 59 57 65 63 61 67 69 73 71 75 -12 -8 -6 -10 -4-20246810 spurious-free dynamic range vs. clock power max106 toc15 clock power per side (dbm) sfdr (db) single-ended clock drive differential clock drive f in = 125mhz, -1dbfs 65 67 66 70 69 68 71 72 74 73 75 spurious-free dynamic range vs. v ee max106 toc17 v ee (v) sfdr (db) -4.50 -5.30 -4.70 -5.50 -4.90 -5.10 f in = 125mhz, -1dbfs typical operating characteristics (continued) (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 600msps, t a = +25?, unless other- wise noted.) 75 10 100 1000 spurious-free dynamic range vs. analog input frequency (single-ended analog input drive) max106 toc09 analog input frequency (mhz) sfdr (db) 50 60 65 55 70 -12dbfs -6dbfs -1dbfs
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 8 _______________________________________________________________________________________ -70 -68 -69 -66 -67 -64 -65 -63 -61 -62 -60 4.50 4.70 4.90 5.10 5.30 5.50 total harmonic distortion vs. v cc i = v cc a = v cc d max106 toc19 v cc (v) thd (db) -128.0 -102.4 -51.2 -76.8 -25.6 0 0 120 60 180 240 300 fft plot (f in = 125.1708984mhz, record length 8192) max106 toc20 analog input frequency (mhz) amplitude (db) h3 h2 enob = 7.75 bits snr = 47.5db thd = -68.8db sfdr = 70.8db fundamental -128.0 -102.4 -51.2 -76.8 -25.6 0 0 120 60 180 240 300 fft plot (f in = 304.4677734mhz, record length 8192) max106 toc21 analog input frequency (mhz) amplitude (db) h2 enob = 7.67 bits snr = 47.2db thd = -56.8db sfdr = 57.4db fundamental h3 -128.0 -102.4 -51.2 -76.8 -25.6 0 0 120 60 180 240 300 fft plot (f in = 1001.8798828mhz, record length 8192) max106 toc22 analog input frequency (mhz) amplitude (db) h3 h2 enob = 7.48 bits snr = 46.0db thd = -52.9db sfdr = 54.7db fundamental 0 -1 -2 -3 -4 -5 500 1500 2500 analog input bandwidth full-power max106toc25 analog input frequency (mhz) amplitude (db) full-power bandwidth = 2.2ghz -128.0 -102.4 -51.2 -76.8 -25.6 0 0 120 60 180 240 300 two-tone intermodulation distortion fft plot (record length 8192, -7db below full-scale) max106 toc23 analog input frequency (mhz) amplitude (db) f 1 = 123.9990235mhz f 2 = 126.0498047mhz sfdr = 61.6db f 1 f 2 (2 x f 2 ) - f 1 (2 x f 1 ) - f 2 -5 -6 -7 -8 -9 -10 500 1500 2500 analog input bandwidth -6db below full-scale max106toc24 analog input frequency (mhz) amplitude (db) small-signal bandwidth = 2.4ghz -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 integral nonlinearity vs. output code (low-frequency servo-loop data) max106 toc26 output code inl (lsb) 0 32 64 96 128 160 192 224 256 -70 -68 -69 -65 -66 -67 -64 -63 -61 -62 -60 total harmonic distortion vs. v ee max106 toc18 v ee (v) thd (db) -4.50 -5.30 -4.70 -5.50 -4.90 -5.10 f in = 125mhz, -1dbfs typical operating characteristics (continued) (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 600msps, t a = +25?, unless other- wise noted.)
-0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 differential nonlinearity vs. output (low-frequency servo-loop data) max106 toc27 output code dnl (lsb) 0 32 64 96 128 160 192 224 256 max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier _______________________________________________________________________________________ 9 pin description dready 200mv/div data 200mv/div dready rise/fall time, data rise/fall time max106 toc28 500ps/div 1.0 1.1 1.2 1.3 1.4 1.5 0 1000 500 1500 2000 2500 voltage standing-wave ratio vs. analog input frequency max106 toc29 analog input frequency (mhz) vswr test point. do not connect . testpoint (t.p.) a10, e17, f2, p3, r17, r18 digital ground gndd a11, b11, b16, b17, c11, c16, u9, u17, v9, v17, v18, w9 pecl supply voltage, +3v to +5v v cc o a12?19, b19, c19, d19, e19, f19, g19, h19, j19, k19, l19, m19, n19, p19, t19, u19, v19, w10?19 analog supply voltage, +5v. supplies analog comparator array. v cc a a9, b9, c9, u7, v7, w7 analog ground?or comparator array. gnda a8, b8, c8, u6, v6, w6 contact analog supply voltage, +5v. supplies t/h amplifier, clock distribu- tion, bandgap reference, and reference amplifier. v cc i a5, b5, c5, h2, h3, m2, m3, u5, v5, w5 analog ground?or t/h amplifier, clock distribution, bandgap refer- ence, and reference amplifier. gndi a1?4, a6, a7, b1, b2, c1, c2, d1, d2, d3, g1, h1, j2, j3, k1, k2, k3, l2, l3, m1, n1, t2, t3, u1, v1, v2, w1?4 function name typical operating characteristics (continued) (v cc a = v cc i = v cc d = +5.0v, v ee = -5.0v, v cc o = +3.3v, refin connected to refout, f s = 600msps, t a = +25?, unless other- wise noted.)
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 10 ______________________________________________________________________________________ pin description (continued) contact analog supply voltage, -5v. supplies t/h amplifier, clock distribu- tion, bandgap reference, and reference amplifier. v ee b3, b4, c3, c4, e3, f3, g2, g3, n2, n3, u2, u3, u4, v3, v4 function name reference ground. must be connected to gndi . gndr b6, b7 primary output data bit 0 (lsb) p0+ b12 digital supply voltage, +5v v cc d b10, b18, c10, c17, c18, t17, t18, u8, u18, v8, w8 primary output data bit 1 p1+ b14 reference input refin c6 auxiliary output data bit 1 a1+ b15 auxiliary output data bit 0 (lsb) a0+ b13 complementary primary output data bit 0 (lsb) p0- c12 complementary primary output data bit 1 p1- c14 complementary auxiliary output data bit 0 (lsb) a0- c13 ttl/cmos demux divide-selection input 1: decimation div4 mode 0: demultiplexed div2 mode divselect d17 die temperature measurement test point. see die temperature measurement section. iconst e1 tie to v cc o to power the auxiliary port. tie to gndd to power down. auxen2 d18 complementary auxiliary output data bit 1 a1- c15 reference output refout c7 die temperature measurement test point. see die temperature measurement section. iptat e2 offset adjust input vosadj f1 ttl/cmos demux enable control 1: enable demux 0: disable demux demuxen e18 primary output data bit 2 p2+ f18 auxiliary output data bit 2 a2+ g18 complementary auxiliary output data bit 2 a2- g17 complementary primary output data bit 2 p2- f17 complementary primary output data bit 3 p3- h17 primary output data bit 3 p3+ h18
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 11 pin description (continued) differential input voltage (-) vin- j1 auxiliary output data bit 3 a3+ j18 primary output data bit 4 p4+ l18 complementary primary output data bit 4 p4- l17 complementary auxiliary output data bit 3 a3- j17 auxiliary output data bit 4 a4+ m18 primary output data bit 5 p5+ n18 complementary primary output data bit 5 p5- n17 contact complementary auxiliary output data bit 5 a5- p17 function name this contact must be connected to gndi. testpoint (t.p.) p2 complementary sampling clock input clk- p1 complementary auxiliary output data bit 4 a4- m17 auxiliary output data bit 5 a5+ p18 50 clock termination return clkcom r1, r2, r3 sampling clock input clk+ t1 complementary pecl reset output rstout- u11 complementary pecl demux reset input rstin- u10 tie to v cc o to power the auxiliary port. tie to gndd to power down. auxen1 r19 complementary pecl overrange bit or- u12 complementary primary output data bit 7 (msb) p7- u14 complementary primary output data bit 6 p6- u16 complementary auxiliary output data bit 6 a6- u15 complementary auxiliary output data bit 7 (msb) a7- u13 pecl reset output rstout+ v11 pecl demux reset input rstin+ v10 pecl overrange bit or+ v12 primary output data bit 7 (msb) p7+ v14 primary output data bit 6 p6+ v16 auxiliary output data bit 6 a6+ v15 auxiliary output data bit 7 (msb) a7+ v13 complementary data-ready clock dready- k17 differential input voltage (+) vin+ l1 data-ready clock dready+ k18
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 12 ______________________________________________________________________________________ detailed description the max106 is an 8-bit, 600msps flash adc with on- chip t/h amplifier and differential pecl-compatible outputs. the adc (figure 1) employs a fully differential 8-bit quantizer and a unique encoding scheme to limit metastable states to typically one error per 10 27 clock cycles, with no error exceeding 1lsb max. an integrated 8:16 output demultiplexer simplifies inter- facing to the part by reducing the output data rate to one-half the sampling clock rate. this demultiplexer has internal reset capability that allows multiple max106s to be time-interleaved to achieve higher effective sampling rates. when clocked at 600msps, the max106 provides a typ- ical effective number of bits (enob) of 7.6 bits at an analog input frequency of 300mhz. the analog input of the max106 is designed for differential or single-ended use with a ?50mv full-scale input range. in addition, this fast adc features an on-board +2.5v precision bandgap reference. if desired, an external reference can also be used. clk- rstin+ rstin- vosadj bandgap reference +2.5v clk+ clkcom vin- vin+ ref out ref in demuxen divselect demux clock driver 16 50 w 50 w 50 w 50 w rstout a0?7 p0?7 dready or differential pecl outputs t/h clock driver adc clock driver reference amplifier 2 2 demux clock generator reset input dual latch reset pipeline gndi gndi gndr delayed reset 16 16 2 2 t/h amplifier logic clock driver bias currents overrange bit auxiliary data port primary data port data ready clock demux reset output 8-bit flash adc max106 figure 1. simplified functional diagram
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 13 principle of operation the max106? flash or parallel architecture provides the fastest multibit conversion of all common integrated adc designs. the key to this high-speed flash archi- tecture is the use of an innovative, high-performance comparator design. the flash converter and down- stream logic translate the comparator outputs into a parallel 8-bit output code and pass this binary code on to the optional 8:16 demultiplexer, where primary and auxiliary ports output pecl-compatible data at up to 300msps per port (depending on how the demultiplex- er section is set on the max106). the ideal transfer function appears in figure 2. on-chip track/hold amplifier as with all adcs, if the input waveform is changing rapidly during conversion, enob and signal-to-noise ratio (snr) specifications will degrade. the max106? on-chip, wide-bandwidth (2.2ghz) t/h amplifier reduces this effect and increases the enob performance signifi- cantly, allowing precise capture of fast analog data at high conversion rates. the t/h amplifier buffers the input signal and allows a full-scale signal input range of ?50mv. the t/h ampli- fier? differential 50 input termination simplifies inter- facing to the max106 with controlled impedance lines. figure 3 shows a simplified diagram of the t/h amplifier stage internal to the max106. aperture width, delay, and jitter (or uncertainty) are parameters that affect the dynamic performance of high-speed converters. aperture jitter, in particular, directly influences snr and limits the maximum slew rate (dv/dt) that can be digitized without a significant contribution of errors. the max106? innovative t/h amplifier design typically limits aperture jitter to less than 0.5ps. aperture width aperture width (t aw ) is the time the t/h circuit requires (figure 4) to disconnect the hold capacitor from the input circuit (for instance to turn off the sampling bridge and put the t/h unit in hold mode). aperture jitter aperture jitter (t aj ) is the sample-to-sample variation (figure 4) in the time between the samples. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 4). (-fs + 1lsb) 0 (+fs - 1lsb) +fs overrange + 255 255 254 129 128 127 126 3 2 1 0 analog input digital output to comparators to comparators buffer amplifier input amplifier clock splitter all inputs are esd protected (not shown in this simplified drawing). sampling bridge gndi 50 w 50 w vin+ vin- gndi c hold 50 w 50 w clk+ clk- clkcom figure 3. internal structure of the 2.2ghz t/h amplifier hold clk analog input sampled data (t/h) t/h t aw t ad t aj track track aperture delay (t ad ) aperture width (t aw ) aperture jitter (t aj ) clk figure 4. t/h aperture timing figure 2. transfer function
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 14 ______________________________________________________________________________________ internal reference the max106 features an on-chip +2.5v precision bandgap reference that can be used by connecting refout to refin. this connects the reference output to the positive input of the reference buffer. the buffer? negative input is internally tied to gndr. gndr must be connected to gndi on the user? application board. refout can source up to 2.5ma to supply external devices if required. an adjustable external reference can be used to adjust the adc? full-scale range. to use an external refer- ence supply, connect a high-precision reference to the refin pin and leave the refout pin floating. in this configuration, refout must not be simultaneously connected at any time, to avoid conflicts between the two references. refin has a typical input resistance of 5k and accepts input voltages of +2.5v ?00mv. using the max106? internal reference is recommend- ed for best performance. digital outputs the max106 provides data in offset binary format to dif- ferential pecl outputs. a simplified circuit schematic of the pecl output cell is shown in figure 5. all pecl out- puts are powered from v cc o, which may be operated from any voltage between +3.0v to v cc d for flexible interfacing with either +3.3v or +5v systems. the nomi- nal v cc o supply voltage is +3.3v. all pecl outputs on the max106 are open-emitter types and must be terminated at the far end of each transmission line with 50 to v cc o - 2v. table 1 lists all max106 pecl outputs and their functions. demultiplexer operation the max106 features an internal data demultiplexer, which provides for three different modes of operation (see the following sections on demultiplexed div2 mode, non-demultiplexed div1 mode , and decimation div4 mode ) controlled by two ttl/cmos-compatible inputs: demuxen and divselect. demuxen enables or disables operation of the internal 1:2 demultiplexer. a logic high on demuxen activates the internal demultiplexer, and a logic low deactivates it. with the internal demultiplexer enabled, divselect controls the selection of the operational mode. divse- lect low selects demultiplexed div2 mode, and div- select high selects decimation div4 mode (table 2). auxiliary-port differential outputs from lsb to msb. a ??indicates the true value; a ? denotes the complementary outputs. a0+ to a7+, a0- to a7- overrange true and complementary outputs or+, or- data-ready clock true and complementary outputs. these signal lines are used to latch the output data from the primary to the auxiliary output ports. data changes on the rising edge of the dready clock. dready+, dready- reset output true and complementary outputs rstout+, rstout- pecl output signals primary-port differential outputs from lsb to msb. a ??indicates the true value; a ? denotes the complementary outputs. p0+ to p7+, p0- to p7- function diff. pair 500 w 500 w 1.8ma gndd gndd gndd v cc o a_+/p_+ a_-/p_- figure 5. simplified pecl output structure table 1. pecl output functions
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 15 non-demultiplexed div1 mode the max106 may be operated at up to the full sam- pling rate (600msps) in non-demultiplexed div1 mode (table 2). in this mode, the internal demultiplexer is dis- abled and sampled data is presented to the primary port only, with the data repeated at the auxiliary port, but delayed by one clock cycle (figure 6). since the auxiliary output port contains the same data stream as the primary output port, the auxiliary port can be shut down to save power by connecting auxen1 and auxen2 to digital ground (gndd). this powers down the internal bias cells and causes both outputs (true and complementary) of the auxiliary port to pull up to a logic-high level. to save additional power, the external 50 termination resistors connected to the pecl termi- nation power supply (v cc o - 2v) may be removed from all auxiliary output ports. demultiplexed div2 mode the max106 features an internally selectable div2 mode (table 2) that reduces the output data rate to one-half of the sample clock rate. the demultiplexed outputs are presented in dual 8-bit format with two con- secutive samples appearing in the primary and auxil- iary output ports on the rising edge of the data-ready clock (figure 7). the auxiliary data port contains the previous sample, and the primary output contains the most recent data sample. auxen1 and auxen2 must be connected to v cc o to power up the auxiliary port pecl output drives. note: the auxiliary port data is delayed one additional clock cycle from the primary port data. grounding auxen1 and auxen2 will power down the auxiliary port to save power. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready auxiliary data port primary data port dready+ dready- figure 6. non-demuxed, div1-mode timing diagram note: the latency to the primary port is 7.5 clock cycles, and the latency to the auxiliary port is 8.5 clock cycles. both the primary and auxiliary data ports are updated on the rising edge of the dready+ clock. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n+1 n-1 n+3 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready auxiliary data port primary data port dready+ dready- n n+2 n+4 figure 7. demuxed div2-mode timing diagram
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 16 ______________________________________________________________________________________ decimation div4 mode the max106 also offers a special decimated, demulti- plexed output (figure 8) that discards every other input sample and outputs data at one-quarter the input sam- pling rate for system debugging at slower output data rates. with an input clock of 600mhz, the effective out- put data rate will be reduced to 150mhz per output port in the div4 mode (table 2). since every other sample is discarded, the effective sampling rate is 300msps. overrange operation a single differential pecl overrange output bit (or+, or-) is provided for both primary and auxiliary demulti- plexed outputs. the operation of the overrange bit depends on the status of the internal demultiplexer. in demultiplexed div2 mode and decimation div4 mode, the or bit will flag an overrange condition if either the primary or auxiliary port contains an overranged sam- ple (table 2). in non-demultiplexed div1 mode, the or port will flag an overrange condition only when the pri- mary output port contains an overranged sample. applications information single-ended analog inputs the max106 t/h amplifier is designed to work at full speed for both single-ended and differential analog inputs (figure 9). inputs vin+ and vin- feature on-chip, laser-trimmed 50 termination resistors to provide excellent voltage standing-wave ratio (vswr) perfor- mance. note: the latency to the primary port remains 7.5 clock cycles, while the latency of the auxiliary port increases to 9.5 clock cycl es. this effectively discards every other sample and reduces the output data rate to 1/4 the sample clock rate. clk- clk+ n n+1 n+2 n+3 n+4 n+5 n-2 n+2 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready auxiliary data port primary data port dready+ dready- n n+4 figure 8. decimation div4-mode timing diagram table 2. demultiplexer operation flags overrange data appearing in the pri- mary port only. low high demuxen overrange-bit operation x low divselect div1 600msps/port div2 300msps/port demux mode high flags overrange data appearing in either the primary or auxiliary port. high div4 150msps/port x = don? care
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 17 in a typical single-ended configuration, the analog input signal (figure 10a) enters the t/h amplifier stage at the in-phase input (vin+), while the inverted phase input (vin-) is reverse-terminated to gndi with an external 50 resistor. single-ended operation allows for an input amplitude of ?50mv. table 3 shows a selec- tion of input voltages and their corresponding output codes for single-ended operation. differential analog inputs to obtain a full-scale digital output with differential input drive (figure 10b), 250mvp-p must be applied between vin+ and vin- (vin+ = +125mv and vin- = -125mv). midscale digital output codes (01111111 or 10000000) occur when there is no voltage difference between vin+ and vin-. for a zero-scale digital output code, the in-phase input (vin+) must see -125mv and the invert- ed input (vin-) must see +125mv. a differential input drive is recommended for best performance. table 4 represents a selection of differential input voltages and their corresponding output codes. +2.8v 50 w 50 w vin+ analog inputs are esd protected (not shown in this simplified drawing). vin- gndi v ee figure 9. simplified analog input structure (single-ended/ differential) v in+ v in- 0v +250mv -250mv t 500mvp-p fs analog input range v in = ?50mv 500mv figure 10a. single-ended analog input signals v in+ v in- +125mv -125mv t 250mv fs analog input range 0v 250mv -250mv figure 10b. differential analog input signals table 3. ideal input voltage and output code results for single-ended operation 0v 11111111 (full scale) +250mv vin- 1 overrange bit vin+ output code 0v 11111111 +250mv - 1lsb 0 0v 0v 01111111 toggles 10000000 0v 0 00000001 -250mv + 1lsb 0 0v 00000000 (zero scale) -250mv 0
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 18 ______________________________________________________________________________________ offset adjust the max106 provides an analog input (vosadj) to com- pensate for system offsets. the offset adjust input is a self-biased voltage divider from the internal +2.5v preci- sion reference. the nominal open-circuit voltage is one- half the reference voltage. with an input resistance of typically 25k , this pin may be driven by an external 10k potentiometer (figure 11) connected between refout and gndi to correct for offset errors. this con- trol provides a typical ?.5lsb offset adjustment range. clock operation the max106 clock inputs are designed for either sin- gle-ended or differential operation (figure 12) with flexi- ble input drive requirements. each clock input is terminated with an on-chip, laser-trimmed 50 resistor to clkcom (clock-termination return). the clkcom termination voltage can be connected anywhere between ground and -2v for compatibility with standard ecl drive levels. the clock inputs are internally buffered with a preampli- fier to ensure proper operation of the data converter, even with small-amplitude sine-wave sources. the max106 was designed for single-ended, low-phase- noise sine-wave clock signals with as little as 100mv amplitude (-10dbm). this eliminates the need for an external ecl clock buffer and its added jitter. single-ended clock inputs (sine-wave drive) excellent performance is obtained by ac- or dc-cou- pling a low-phase-noise sine-wave source into a single clock input (figure 13a, table 5). for proper dc bal- ance, the undriven clock input should be externally 50 reverse-terminated to gndi. table 4. ideal input voltage and output code results for differential operation -125mv -125mv + 0.5lsb 11111111 (full scale) +125mv vin- 1 11111111 +125mv - 0.5lsb 0 overrange bit 0v +125mv - 0.5lsb 01111111 toggles 10000000 0v 0 00000001 -125mv + 0.5lsb 0 +125mv 00000000 (zero scale) -125mv 0 vin+ output code gndi 10k pot refout vosadj max106 figure 11. offset adjust with external 10k potentiometer clk+ clk inputs are esd protected (not shown in this simplified drawing). clkcom clk- 50 w +0.8v 50 w gndi v ee figure 12. simplified clock input structure (single-ended/ differential)
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 19 the dynamic performance of the data converter is essentially unaffected by clock-drive power levels from -10dbm (100mv clock signal amplitude) to +10dbm (1v clock signal amplitude). the max106 dynamic per- formance specifications are determined by a single- ended clock drive of +4dbm (500mv clock signal amplitude). to avoid saturation of the input amplifier stage, limit the clock power level to a maximum of +10dbm. differential clock inputs (sine-wave drive) the advantages of differential clock drive (figure 13b, table 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. the precision on-chip laser-trimmed 50 clock-termination resistors ensure excellent amplitude matching. see single-ended clock inputs (sine-wave drive) for proper input amplitude requirements. single-ended clock inputs (ecl drive) configure the max106 for single-ended ecl clock drive by connecting the clock inputs as shown in figure 13c (table 5). a well-bypassed v bb supply (-1.3v) is essential to avoid coupling noise into the undriven clock input, which would degrade the dynamic perfor- mance. differential clock inputs (ecl drive) the max106 may be driven from a standard differential (figure 13d, table 5) ecl clock source by setting the clock termination voltage at clkcom to -2v. bypass the clock-termination return (clkcom) as close to the adc as possible with a 0.01? capacitor connected to gndi. clk+ clk- = 0v +0.5v -0.5v note: clkcom = 0v t figure 13a. single-ended clock input signals clk+ -0.8v -1.8v t clk- = -1.3v note: clkcom = -2v figure 13c. single-ended ecl clock drive clk+ clk- +0.5v -0.5v t note: clkcom = 0v figure 13b. differential clock input signals clk+ clk- -0.8v -1.8v t note: clkcom = -2v figure 13d. differential ecl clock drive
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 20 ______________________________________________________________________________________ ac-coupling clock inputs the clock inputs clk+ and clk- can also be driven with positive referenced ecl (pecl) logic levels if the clock inputs are ac-coupled. under this condition, con- nect clkcom to gndi. single-ended ecl/pecl/sine- wave drive is also possible if the undriven clock input is reverse-terminated to gndi through a 50 resistor in series with a capacitor whose value is identical to that used to couple the driven input. demux reset operation the max106 features an internal 1:2 demultiplexer that reduces the data rate of the output digital data to one- half the sample clock rate. demux reset is necessary when interleaving multiple max106s and/or synchroniz- ing external demultiplexers. the simplified block dia- gram of figure 1 shows that the demux reset signal path consists of four main circuit blocks. from input to out- put, they are the reset input dual latch, the reset pipeline, the demux clock generator, and the reset out- put. the signals associated with the demux reset opera- tion and the control of this section are listed in table 6 . reset input dual latch the reset input dual-latch circuit block accepts differ- ential pecl reset inputs referenced to the same v cc o power supply that powers the max106 pecl outputs. for applications that do not require a synchronizing reset, the reset inputs can be left open. in this case, they will self-bias to a proper level with internal 50k resistors and a 20? current source. this combination creates a -1v difference between rstin+ and rstin- to disable the internal reset circuitry. when driven with pecl logic levels terminated with 50 to (v cc o - 2v), the internal biasing network can easily be overdriven. figure 14 shows a simplified schematic of the reset input structure. to properly latch the reset input data, setup (t su ) and data-hold times (t hd ) must be met with respect to the rising edge of the sample clock. the timing diagram of figure 15 shows the timing relationship of the reset input and sampling clock. table 5. dc-coupled clock drive options -10dbm to +4dbm figure 13a single-ended sine wave clk+ gndi clkcom clock drive reference external 50 to gndi clk- -10dbm to +4dbm -10dbm to +4dbm figure 13b differential sine wave gndi ecl drive -1.3v figure 13c single-ended ecl -2v ecl drive ecl drive figure 13d differential ecl -2v 50k 50k rstin+ rstin- reset inputs are esd protected (not shown on this simplified drawing). 20 m a gndd v cc o figure 14. simplified reset input structure rstin+ 50% 50% clk+ clk- rstin- 50% t su t hd figure 15. reset input timing definitions
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 21 reset pipeline the next section in the reset signal path is the reset pipeline. this block adds clock latency cycles to the reset signal to match the latency of the converted ana- log data through the adc. in this way, when reset data arrives at the rstout+/rstout- pecl output it will be time-aligned with the analog data present in the prima- ry and auxiliary ports at the time the reset input was deasserted at rstin+/rstin-. demux clock generator the demux clock generator creates the div1, div2, or div4 clocks required for the different modes of demux and non-demux operation. the ttl/cmos control inputs demuxen and divselect control the demuxed mode selection, as described in table 2. the timing diagrams in figures 16 and 17 show the output timing and data alignment in div1, div2, and div4 modes, respectively. the phase relationship between the sampling clock at the clk+/clk- inputs and the data-ready clock at the dready+/dready- outputs will be random at device power-up. as with all divide-by-two circuits, two possi- ble phase relationships exist between these clocks. the difference between the phases is the inversion of the div2/dready clock. the timing diagram in figure 16 shows this relationship. reset all max106 devices to a known dready phase after initial power-up for applications such as interleav- ing, where two or more max106 devices are used to achieve higher effective sampling rates. this synchro- nization is necessary to set the order of output samples between the devices. resetting the converters accom- plishes this synchronization. the reset signal is used to force the internal counter in the demux clock-generator block to a known phase state. table 6. demux operating and reset control signal 50% clk+ clk- dready + dready - "phase 1" "phase 2" 20% 20% 50% 80% 80% t pd1 dready- dready+ t rdready t fdready dready + dready - figure 16. clk and dready timing in demuxed div2 mode showing two possible dready phases clk+ clk- dready + dready - auxiliary port data primary port data t pwh t pwl t pd1 t pd2 figure 17. output timing for all modes (div1, div2, div4) sampling clock inputs master adc timing signal. the adc samples on the rising edge of clk+. clk+, clk- type differential pecl outputs data-ready pecl output. output data changes on the rising edge of dready+. dready+, dready- differential pecl inputs demux reset input signals. resets the internal demux when asserted. rstin+, rstin- differential pecl outputs reset outputs?or resetting additional external demux devices. rstout+, rstout- signal name function
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 22 ______________________________________________________________________________________ reset output finally, the reset signal is presented in differential pecl format to the last block of the reset signal path. rstout+/rstout- output the time-aligned reset sig- nal used for resetting additional external demuxes in applications where further reduction in the output data rate is desired. many demux devices require their reset signal to be asserted for several clock cycles while they are clocked. to accomplish this, the max106 dready clock will continue to toggle while rstout is asserted. when a single max106 device is used, no synchroniz- ing reset is required since the order of the samples in the output ports is unchanged regardless of the phase of the dready clock. in div2 mode, the data in the auxiliary port is delayed by 8.5 clock cycles while the data in the primary port is delayed by 7.5 clock cycles. the older data is always in the auxiliary port, regardless of the phase of the dready clock. the reset output signal, rstout, is delayed by one fewer clock cycle (6.5 clock cycles) than the primary port. the reduced latency of rstout serves to mark the start of synchronized data in the primary and auxil- iary ports. when the rstout signal returns to a zero, the dready clock phase is reset. since there are two possible phases of the dready clock with respect to the input clock, there are two pos- sible timing diagrams to consider. the first timing dia- gram (figure 18) shows the rstout timing and data alignment of the auxiliary and primary output ports when the dready clock phase is already reset. for this example, the rstin pulse is two clock cycles long. under this condition, the dready clock continues uninterrupted, as does the data stream in the auxiliary and primary ports. the second timing diagram (figure 19) shows the results when the dready phase is opposite from the reset phase. in this case, the dready clock ?wallows a clock cycle of the sample clock, resynchronizing to the reset phase. note that the data stream in the auxil- iary and primary ports has reversed. before reset was note: the latency to the reset output is 6.5 clock cycles. the latency to the primary port is 7.5 clock cycles, and the latency to the auxiliary port is 8.5 clock cycles. all data ports are updated on the rising edge of the dready + clock. clk- clk+ t su t hd n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clk dready dready+ dready- rstin+ rstin- rstout+ rstout- reset input n+1 n-1 n+3 auxiliary data port primary data port n n+2 n+4 reset out data port figure 18. reset output timing in demuxed div2 mode (dready aligned)
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 23 asserted, the auxiliary port contained ?ven?samples while the primary port contained ?dd?samples. after rstout is deasserted (which marks the start of the dready clock? reset phase), note that the order of the samples in the ports has been reversed. the auxiliary port also contains an out-of-sequence sample. this is a consequence of the ?wallowed?clock cycle that was needed to resynchronize dready to the reset phase. also note that the older sample data is always in the aux- iliary port, regardless of the dready phase. these examples show the combinations that result with a reset input signal of two clock cycles. it is also possi- ble to successfully reset the internal max106 demux with a reset pulse only one clock cycle long, proving the setup-time and hold-time requirements are met with respect to the sample clock. however, this is not rec- ommended when additional external demuxes are used. note that many external demuxes require their reset signals to be asserted while they are clocked, and may require more than one clock cycle of reset. more impor- tantly, if the phase of the dready clock is such that a clock pulse will be ?wallowed?to resynchronize, then no reset output will occur at all. in effect, the rstout signal will be ?wallowed?along with the clock pulse. the best method to ensure complete system reset is to assert rstin for the appropriate number of dready clock cycles required to complete reset of the external demuxes. die temperature measurement for applications that require monitoring of the die tem- perature, it is possible to determine the die temperature of the max106 under normal operating conditions by observing the currents i const and i ptat , at contacts iconst and iptat. i const and i ptat are two 100? (nominal) currents that are designed to be equal at +27?. these currents are derived from the max106? internal precision +2.5v bandgap reference. i const is designed to be temperature independent, while i ptat is directly proportional to the absolute temperature. these currents are derived from pnp current sources refer- enced from v cc i and driven into two series diodes con- nected to gndi. the contacts iconst and iptat may be left open because internal catch diodes prevent sat- uration of the current sources. the simplest method of note: dready phase was adjusted to match the reset phase by ?wallowing?one input clock cycle. the auxiliary port contains an out-of-sequence sample as a result of the delay. clk- clk+ t su t hd n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 adc sample number adc samples on the rising edge of clk+ clock pulse ?wallowed out-of-sequence sample clk dready dready+ dready- rstin+ rstin- rstout+ rstout- reset input n-1 n+1 n-2 auxiliary data port primary data port n n+2 n+4 reset out data port figure 19. reset output timing in demuxed div2 mode (dready realigned)
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 24 ______________________________________________________________________________________ determining the die temperature is to measure each current with an ammeter (which shuts off the internal catch diodes) referenced to gndi. the die temperature in ? is then calculated by the expression: another method of determining the die temperature uses the operational amplifier circuit shown in figure 20. the circuit produces a voltage that is proportional to the die temperature. a possible application for this signal is speed control for a cooling fan to maintain constant max106 die temperature. the circuit operates by converting the i const and i ptat currents to volt- ages v const and v ptat , with appropriate scaling to account for their equal values at +27?. this voltage difference is then amplified by two amplifiers in an instrumentation-amplifier configuration with adjustable gain. the nominal value of the circuit gain is 4.5092v/v. the gain of the instrumentation amplifier is given by the expression: to calibrate the circuit, first connect pins 2-3 on ju1 to zero the input of the ptat path. with the max106 pow- ered up, adjust potentiometer r3 until the voltage at the v temp output is -2.728v. connecting pins 1-2 on ju1 restores normal operation to the circuit after the calibra- tion is complete. the voltage at the v temp node will then be proportional to the actual max106 die tempera- ture according to the equation: the overall accuracy of the die temperature measure- ment using the operational-amplifier scaling circuitry is limited mainly by the accuracy and matching of the resistors in the circuit. thermal management depending on the application environment for the esbga-packaged max106, the customer may have to apply an external heatsink to the package after board assembly. existing open-tooled heatsinks are available from standard heatsink suppliers (listed in heatsink manufacturers ). the heatsinks are available with preap- plied adhesive for easy package mounting. t ( c) 100 v die temp = a v vv a r r r r v temp const ptat v = - =+ + 1 1 2 2 1 3 t 300 i i 273 die ptat const = ? ? - v const v temp r1 7.5k r2 15k r2 15k 3.32k 5k r1 7.5k 6.65k 6.65k 6.05k 12.1k 12.1k 1 2 3 ju1 10-turn i ptat v ptat i const 1/4 max479 1/4 max479 1/4 max479 1/4 max479 figure 20. die temperature-acquisition circuit with the max479
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 25 thermal performance the max106 has been modeled to determine the thermal resistance from junction to ambient. table 7 lists the adc? thermal performance: ambient temperature: t a = +70? heatsink dimensions: 25mm x 25mm x 10mm pc board size and layout: 4in. x 4in. 2 signal layers 2 power layers heatsink manufacturers aavid engineering and ierc provide open-tooled, low- profile heatsinks, fitting the 25mm x 25mm esbga package. aavid engineering, inc. phone: 714-556-2665 heatsink catalog no.: 335224b00032 heatsink dimensions: 25mm x 25mm x 10mm international electronic research corporation (ierc) phone: 818-842-7277 heatsink catalog no.: bdn09-3cb/a01 heatsink dimensions: 23.1mm x 23.1mm x 9mm bypassing/layout/power supply grounding and power-supply decoupling strongly influ- ence the max106? performance. at 600mhz clock fre- quency and 8-bit resolution, unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections and adversely influence the dynamic performance of the adc. therefore, closely follow the grounding and power-supply decoupling guidelines (figure 22). maxim strongly recommends using a multilayer printed circuit board (pcb) with separate ground and power- supply planes. since the max106 has separate analog and digital ground connections (gnda, gndi, gndr, and gndd, respectively), the pcb should feature sep- arate analog and digital ground sections connected at only one point (star ground at the power supply). digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. high- speed signals, including clocks, analog inputs, and digital outputs, should be routed on 50 microstrip lines such as those employed on the max106 evalua- tion kit. the max106 has separate analog and digital power- supply inputs: v ee (-5v analog and substrate supply) and v cc i (+5v) to power the t/h amplifier, clock distri- bution, bandgap reference, and reference amplifier; v cc a (+5v) to supply the adc? comparator array; v cc o (+3v to v cc d) to establish power for all pecl- based circuit sections; and v cc d (+5v) to supply all logic circuits of the data converter. the max106 v ee supply contacts must not be left open while the part is being powered up. to avoid this condition, add a high-speed schottky diode (such as a motorola 1n5817) between v ee and gndi. this diode prevents the device substrate from forward biasing, which could cause latchup. table 7. thermal performance for max106 with or without heatsink 16.5 0 12.5 14.3 9.4 200 13 8.3 400 12.5 7.4 800 6 8 10 12 14 16 18 0 200 100 300 400 500 600 700 800 thermal resistance vs. airflow airflow (linear ft./min.) q ja ( c/w) with heatsink without heatsink figure 21. max106 thermal performance max106 q ja (?/w) without heatsink with heatsink airflow (linear ft/min)
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 26 ______________________________________________________________________________________ all supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the pcb. for best performance, bypass all power supplies to the appropriate ground with a 10? tantalum capacitor to filter power-supply noise, in parallel with a 0.01? capacitor and a high-quality 47pf ceramic chip capaci- tor located very close to the max106 device, to filter very high-frequency noise. static parameter definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max106 are mea- sured using the best-straight-line fit method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. 10 m f gndd v cc d gnda v cc a gndi v cc i gndi 1n5817 v ee v cc a = +4.75v to +5.25v v cc d = +4.75v to +5.25v v cc i = +4.75v to +5.25v v cc o = +3.0v to v cc d v ee = -4.75v to -5.25v note: locate all 47pf capacitors as close as possible to the max106 device. gndd v cc o 10nf 10nf 47pf 47pf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 47pf 47pf 10 m f 10nf 10nf 47pf 47pf 47pf 47pf figure 22. max106 bypassing and grounding
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 27 bit error rates (bers) errors resulting from metastable states may occur when the analog input voltage (at the time the sample is taken) falls close to the decision point of any one of the input comparators. here, the magnitude of the error depends on the location of the comparator in the com- parator network. if it is the comparator for the msb, the error will reach full scale. the max106? unique encod- ing scheme solves this problem by virtually eliminating these errors. dynamic parameter definitions signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, the theoretical maximum (snr) is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr (max) = (6.02 n + 1.76) db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. effective number of bits enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob is computed from a curve fit referenced to the theoreti- cal full-scale range. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is computed from the enob as follows: sinad = (6.02 enob) + 1.76 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio, expressed in decibels, of the rms amplitude of the fun- damental (maximum signal component) to the rms value of the next-largest spurious component, exclud- ing dc offset. intermodulation distortion the two-tone intermodulation distortion (imd) is the ratio, expressed in decibels, of either input tone to the worst 3rd-order (or higher) intermodulation products. the input tone levels are at -7db full scale. thd 20 log v v v v / v 2 2 3 2 4 2 5 2 1 =+++ ? ? ? ? ? ? ? chip information transistor count: 20,486 substrate connected to v ee
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 28 ______________________________________________________________________________________ typical operating circuit max106 p7 p6 p5 p4 p3 p2 p1 p0 to memory or digital signal processor 2 or v ee v cc av cc iv cc dv cc o auxen1 auxen2 -5v analog divselect demuxen +5v vosadj vin- clk+ clk- clkcom rstin+ rstin- +5v analog +5v digital +3.3v digital dready rstout primary pecl outputs 2 2 2 2 2 2 2 2 2 2 a7 a6 a5 a4 a3 a2 a1 a0 2 2 2 2 2 2 2 2 auxilary pecl outputs gnda gndi gndi gndr gndi gndd refout refin z 0 = 50 w z 0 = 50 w vin+ differential analog input 500mvp-p fs sample clock 600mhz +4dbm z 0 = 50 w 50 w z 0 = 50 w 50 w all outputs must be terminated like this. v cc o - 2v
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 29 top view max106 max106 192 ball esbga printed circuit board (pcb) land pattern 192-contact esbga pcb land pattern
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier 30 ______________________________________________________________________________________ package information super bga.eps
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier ______________________________________________________________________________________ 31 package information (continued)
max106 ?v, 600msps, 8-bit adc with on-chip 2.2ghz bandwidth track/hold amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

▲Up To Search▲

Price & Availability of MAX106CHC

	To Download MAX106CHC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .